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NCP1910
maximum sink and source of output current capability
of OTA is around 30 m A. Due to the “V out Low Detect”
block (VLD), when the V FB is below 95% V PREF , an
extra 200 m A current source (I VLD in Figure 52) will
raise V CTRL rapidly. Hence prevent the PFC output
from dropping too low and improve the transient
50
0
response performance. The relationship between
current flowing in/out V CTRL pin and V FB is as shown
in Figure 53.
It is recommended to add a typical 100 pF capacitor C FB
decoupling capacitor next to feedback pin to prevent from
noise impact.
? 50 2
2.2
2.4
2.6
2.8
3
? 100
? 150
? 200
? 250
230 m A raises V CTRL rapidly
when V FB is below 95%
V PREF
No DRV when V FB is
above 105% V PREF
V FB
Figure 53. V FB vs. Current Flowing in/out From V CTRL Pin
PFCok Signal
The PFC provides a “PFCok” signal to:
? enable the dynamic response enhancer (I VLD ) if V bulk is
below 95%, finish of the PFC soft ? start,
? enable the PFC frequency foldback,
? enable the timer (t DEL1 ), which is to start the LLC ? HB
converter,
? enable the timer (t DEL2 ), which is to stop LLC ? HB
converter once “PFCok” is asserted low or V bulk is
lower than PG level after LLC ? HB has started.
Refer to Figure 54. “PFCok” signal is low when
? the PFC stage start ? up, or
? any latch off signal arrives, or
? line brown ? out activates.
“PFCok” signal is high when
? DRV starts operating and the PFC stage is above 95%
of target, i.e. the VLD comparator output is high, or
? the PFC stage is above 100% target, i.e. PFC REG
comparator output is high.
This “PFCok” signal is high when the PFC stage is in
normal operation, i.e. its output is above 95% of normal
output, and low otherwise.
PFC_BO
Latch
Grand Reset
R
Q
Q
PFC_OK
95% V PREF
+
?
DRV
VLD
S
FB
+
V PREF
?
PFC REG
Figure 54. PFCok Signal Block Diagram
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